1. Field of the Invention
This invention relates to microprocessors. In particular, the invention relates to cache memory.
2. Background of the Invention
Practical chipset caches need to exceed the size of the caches in the processor with which they are paired in order to achieve substantial performance improvements. Desktop processors may be expected to deploy internal caches that can retain up to several megabytes (MB) of information. Consequently, the chipset caches may need to contain up to ten times that amount (e.g., 8 MB) of data storage. With this enormous amount of storage, the control tasks including the cache tag store would be proportionally complex.
Existing techniques integrate the control functions of the caches within the same chipset. Although these techniques may be adequate for small to medium cache size (e.g., less than 1 MB), for large cache sizes, these techniques may lead to inefficiency use of resources and prolonged design cycle. Chipsets are often designed on a standard cell or gate array process. Complex custom logic blocks may be difficult to integrate into chipset designs.